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Showing results 116 to 135 of 148

Article

Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process SchemeSCIESCOPUS

IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 67, no. 7, page. 2732 - 2737, 2020-07

Conference

Reliability of HfO2/SiO2 Dielectric with Strain Engineering using CESL Stressor

IEEE Nanotechnology Materials and Devices Conference (NMDC2008), 2008-10-20

Conference

Reliability of HfO2/SiO2 Dielectric with Strain Engineering using CESL Stressor

IEEE IRPS(2009), 2009-04-26

Conference

Reliable Extraction of Series Resistance in Silicon Nanowire FETs Using Y-function Technique

IEEE Nanotechnology Materials and Devices Conference (NMDC2011), 2011-10-19

Conference

RF and Hot Carrier Effects in metal gate/high-k Dielectric nMOSFETs at cryogenic temperature

IEEE IRPS(2009), 2009-04-26

Conference

RF characteristics for 70 nm MOSFETs below 77K

AWAD 2007, 2007-06-25

Conference

RF characteristics in Metal Gate/High-K Dielectric nMOSFETs at cryogenic temperature

16th Korean Conference on Semiconductors (2009), 2009-02-18

Conference

RF degradation of short channel metal gate/high-k dielectric nMOSFET by hot carrier effect

대한전자공학회 하계학술대회 2009, 2009-07-08

Conference

RF performance degradation in 100-nm metal gate/high-k dielectric nMOSFET by hot carrier effects

ESSDERC 2009, 2009-09-14

Conference

Scalability of OTS Integrated PCM for 3-D Stackable Cross-point Array Structure Using TCAD Simulation

the 17th International Nanotech Symposium & Exhibition, 2019-07-04

Conference

Sensitivity Analysis of Each Inner Spacer Thickness Variation in Sub 3-nm Node Si Nanosheet FETs

제 29회 한국반도체학술대회, 2022-01-25

Article

Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETsSCIESCOPUS

IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 67, no. 1, page. 258 - 262, 2020-01

Conference

Series Resistance Behavior Extracted from Silicon Nanowire Transistors Using the Y-function Technique

Solid State Devices and Materials (SSDM2009), page. 1108 - 1109, 2009-10-06

Conference

Si Gate-All-Around Nanosheet FET: the Key Enabler of 3nm Technology Node

제 28회 반도체학술대회, 2021-01-28

BAEK, ROCK HYUN

Article

Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm NodeSCIESCOPUS

IEEE ACCESS, vol. 7, page. 172290 - 172295, 2019-12

Conference

SRAM Performance Variations Induced by Source/Drain Mole Fraction Change of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors

The 18th International Nanotech Symposium & Exhibition, 2020-07-01

Article

STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact ResistivitySCIESCOPUS

IEEE ELECTRON DEVICE LETTERS, vol. 34, no. 9, page. 1082 - 1084, 2013-09

Conference

Study of continuous-wave RGB laser annealing for the activation of phosphorus/boron-doped Si deep junction with high scan speed

The 7th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2023), 2023-03-09

Conference

Sub-100 nm InGaAs Quantum-Well (QW) MOSFETs with Al2O3/HfO2 (EOT < 1 nm) for Low-Power Logic Applications

IEEE International Electron Devices Meeting, 2013-12-09

Article

Systematic analysis of oxide trap distribution of 4H-SiC DMOSFETs using TSCIS and its correlation with BTI and SILC behaviorSCIESCOPUS

SOLID-STATE ELECTRONICS, vol. 140, page. 18 - 22, 2018-02

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