Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node

Abstract

A novel and feasible process scheme to downsize the source/drain (S/D) epitaxy of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) were introduced by using fully-calibrated TCAD for the first time. The S/D epitaxy formed by selective epitaxial growth was diamond-shaped and occupied a large proportion of the device size irrespective of the active channel area. However, this problem was solved by patterning the low-k regions prior to S/D formation by preventing the lateral overgrowth of S/D epitaxy; the so-called S/D patterning (SDP). Its smaller S/D epitaxy decreased the average longitudinal channel stresses and drive currents for NFETs. However, the small diffusions of the boron dopants into the channel regions improved the short-channel effects and alleviated the drive current reduction for PFETs. Gate capacitances decreased greatly by reducing outer-fringing capacitances between the metal-gate stack and S/D regions. Through SPICE simulation based on the virtual source model, operation frequencies and dynamic powers of 15-stage ring oscillators were studied. SDP FinFETs have better circuit performances than the conventional and bottom oxide bulk FinFETs along with smaller active areas, promising for further area scaling through simple and reliable S/D process.