Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETs

Abstract

Source/drain (S/D) variations in sub-5-nm node fin and nanosheet field-effect transistors (NSFETs) were thoroughly analyzed by using fully calibrated technology computer-aided design (TCAD). S/D open and contact critical dimensions (OCD and CCD) vary during anisotropic etching for silicide and S/D epi formations, respectively, and these vary dc/ac performances. OCD varies S/D resistances and parasitic capacitances, but slight RC delay variations occur. CCD affects OFF-state currents ( ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ ) and RC delay, but differently in terms of fin field-effect transistors (FinFETs) and NSFETs. As the S/D epi enlarges by CCD changes, high subfin leakage of FinFETs flows into the fin bottom regions, thus varying ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ greatly. NSFETs have the dielectric layers beneath the S/D epi; therefore, the ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ variations are smaller. Both effective currents ( ${I}_{{\text {eff}}}$ ) and gate capacitances ( ${C}_{{\text {gg}}}$ ) of FinFETs vary in the same direction, whereas the NSFETs have constant ${C}_{{\text {gg}}}$ with respect to CCD changes because of the tradeoff between the intrinsic and parasitic capacitances. Although this effect increases the RC delay variations of the NSFETs, p-type FinFETs have the largest RC delay variations due to the greatest relative variations of ${I}_{{\text {eff}}}$ . Thus, the NSFETs are much immune to CCD variations compared with FinFETs in terms of ${I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ and RC delay.