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Conference

70nm CMOS BSIM4 Macro modeling for RFIC design

대한전자공학회 하계학술대회 2006, 2006-06-21

Article

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 Gate Stack nMOSFETsSCIESCOPUS

MICROELECTRONIC ENGINEERING, vol. 88, no. 12, page. 3411 - 3414, 2011-12

Article

A new physical 1/f noise model for double stack high-k gate dielectric MOSFETsSCIESCOPUS

IEEE ELECTRON DEVICE LETTERS, vol. 30, no. 12, page. 1365 - 1367, 2009-12

Conference

A Novel Series-resistance Extraction Method for Nano-scaled nMOSFETs Considering Mobility Degradation due to Vbs

IEEE Nanotechnology Materials and Devices Conference (NMDC2008), 2008-10-20

Article

A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile ApplicationsSCIESCOPUS

IEEE ACCESS, vol. 8, page. 196975 - 196978, 2020-10

Article

A Review of Multi-Modal Learning from the Text-Guided Visual Processing ViewpointSCIESCOPUS

Sensors, vol. 22, no. 18, page. 6816, 2022-09

Conference

Accurate Extraction of Volume Trap Density from Si-Nanowire FET using the Newly Developed Cylindrical Coordinate Based 1/f noise model

17th Korean Conference on Semiconductors (2010), 2010-02-24

Conference

An Analysis on Electrical Characteristics of Submicron-LTPS Thin-Film-Transistors

한국반도체디스플레이기술학회 2018년 추계학술대회, 2018-11-22

Article

Analog Figure-of-Merits Comparison of Gate Workfunction Variability and Random Discrete Dopant Between Inversion-Mode and Junctionless Nanowire FETsSCIE

JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, vol. 18, no. 9, page. 6598 - 6601, 2018-09

Conference

Analysis of Bottom Channel Effect in Silicon Nanowire FET based on Bulk-Silicon: Reduction of Parasitic Capacitance caused by SiGe layer

Solid State Devices and Materials (SSDM2011), 2011-09-28

Conference

Analysis of Mechanical Stress on Charge Trap Nitride (CTN) for Program Operation in 3D NAND Flash Memory

제 30회 한국반도체학술대회, 2023-02-15

Conference

Analysis of Parasitic Bottom Capacitance in n- and p-type Si-Nanowire Field Effect Transistors on Bulk

IEEE-NANO (2011), 2011-08-15

Article

Arbitrary Font Generation by Encoder Learning of Disentangled FeaturesSCIESCOPUS

Sensors, vol. 22, no. 6, page. 2374, 2022-03

Conference

BCl3/Cl2 plasma etching process of ferroelectric gate stack for device integration

제 30회 한국반도체학술대회, 2023-02-15

Article

Bottom oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm NodeSCIESCOPUS

IEEE ACCESS, vol. 7, page. 75762 - 75767, 2019-06

Conference

C-V Characteristics and Analysis of Undoped Gate-All-Around Nanowire FET Array

Solid State Devices and Materials (SSDM2010), page. 1277 - 1278, 2010-09-21

Article

C-V Characteristics in Undoped Gate-All-Around Nanowire FET ArraySCIESCOPUS

IEEE Electron Device Letters, vol. 32, no. 2, page. 116 - 118, 2011-02

Conference

Channel Trimming Process to Improve Electro-thermal Characteristics for Sub-3-nm Node Nanosheet Field-Effect Transistors with Laser Spike Annealing

2023 International Conference on Solid State Devices and Materials (SSDM), 2023-09-08

Conference

Characteristics of Gate-All-Around Si-NWFET, including Rsd, Cylindrical Coordinate Based 1/f Noise and Hot Carrier Effects

IEEE IRPS(2010), 2010-05-02

Article

Characteristics of the Series Resistance Extracted From Si Nanowire FETs Using the Y-Function TechniqueSCIESCOPUS

IEEE TRANSACTIONS ON NANOTECHNOLOGY, vol. 9, no. 2, page. 212 - 217, 2010-03

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