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PARK, HONG JUNE(박홍준) scopus

Department: Dept of Electrical Engineering(전자전기공학과)

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Publication & Time Cited Count (For the Last 5 years)

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Date Issued : [2010 TO 2019] Type : Article

Article

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM InterfaceSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 49, no. 11, page. 2618 - 2630, 2014-11

Article

A 0.5-V, 1.47-mu W 40-kS/s 13-bit SAR ADC With Capacitor Error CompensationSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 61, no. 11, page. 840 - 844, 2014-11

Article

An Approximate Closed-Form Channel Model for Diverse Interconnect ApplicationsSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol. 61, no. 10, page. 3034 - 3043, 2014-10

Article

A Single-Stage 37 dB-Linear Digitally-Controlled Variable Gain Amplifier for Ultrasound Medical ImagingSCIESCOPUSKCI

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 14, no. 5, page. 579 - 587, 2014-10

Article

Current-Mode Transceiver for Silicon Interposer ChannelSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 49, no. 9, page. 2044 - 2053, 2014-09

Article

Verilog Modeling of Transmission Line for USB 2.0 High-Speed PHY InterfaceSCIESCOPUS

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 14, no. 4, page. 463 - 470, 2014-08

Article

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias CurrentSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 61, no. 7, page. 481 - 485, 2014-07

Article

An Interleaved Data Acquisition to Reduce Common Noise in Coronary Doppler VibrometrySCIESCOPUS

2014 IEEE INTERNATIONAL ULTRASONICS SYMPOSIUM (IUS), page. 1300 - 1303, 2014-01

Article

A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLLSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 48, no. 11, page. 2795 - 2804, 2013-11

Article

A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog CircuitsSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, vol. 60, no. 11, page. 2845 - 2856, 2013-11

Article

A Channel Model of Scaled RC-dominant Wires for High-Speed Wireline Transceiver DesignSCIESCOPUSKCI

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 13, no. 5, page. 482 - 491, 2013-10

Article

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter CancellationSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 48, no. 9, page. 2118 - 2127, 2013-09

Article

A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based AmplifierSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 60, no. 3, page. 142 - 146, 2013-03

Article

A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-mu m CMOSSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 48, no. 2, page. 516 - 526, 2013-02

Article

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory InterfaceSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 60, no. 2, page. 91 - 95, 2013-02

Article

A 1.9-GHz Fractional-N Digital PLL With Subexponent Delta Sigma TDC and IIR-Based Noise CancellationSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 59, no. 11, page. 721 - 725, 2012-11

Article

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip LinesSCIESCOPUS

IEEE Journal of Solid-State Circuits, vol. 47, no. 9, page. 2068 - 2079, 2012-09

Article

A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping Delta Sigma TDCSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 47, no. 4, page. 875 - 883, 2012-04

Article

A 1.25 ps Resolution 8b Cyclic TDC in 0.13 mu m CMOSSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 47, no. 3, page. 736 - 743, 2012-03

Article

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLLSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 58, no. 10, page. 687 - 691, 2011-10

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