A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL
SCIE
SCOPUS
- Title
- A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL
- Authors
- Dong-Woo Jee; Yunjae Suh,; Kim, B; Park, HJ; Sim, JY
- Date Issued
- 2013-11
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- This paper presents a 1-GHz Delta Sigma fractional-N PLL with a noise-filtering scheme using a FIR-embedded phase interpolator. The proposed dual-referenced interpolation scheme compensates for systematic nonlinearity in circuit operation and increases immunity to mismatches in input seed phases. By multiple use of a dual-referenced interpolator, the phase interpolator realizes an embedded FIR filtering for the quantization noise from the Delta Sigma modulator. The implemented PLL in 0.13-mu m CMOS consumes 16.8 mW and shows a reduction of the phase noise by 34 dB. With 3.2-MHz-wide bandwidth, the proposed filtering technique achieves an in-band noise of -106 dBc at 100 kHz and an out-of-band noise of -107.5 dBc at 6 MHz.
- Keywords
- Delta-sigma modulation; FIR filtering; fractional-N PLL; phase interpolator; phase-locked loop (PLL); phase noise; quantization noise; FREQUENCY-SYNTHESIZER; LOCKED LOOP
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/14575
- DOI
- 10.1109/JSSC.2013.2282620
- ISSN
- 0018-9200
- Article Type
- Article
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 48, no. 11, page. 2795 - 2804, 2013-11
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