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Showing results 81 to 100 of 148

Conference

Investigation of GIDL Behavior in Si-Nanowire FET with Hot Carrier Stress

18th Korean Conference on Semiconductors (2011), 2011-02-16

Article

Investigation of Process-Induced Performance Variability and Optimization of the 10 nm Technology Node Si Bulk FinFETsSCIESCOPUS

SOLID-STATE ELECTRONICS, vol. 96, page. 27 - 33, 2014-06

Article

Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic ApplicationsSCIESCOPUS

IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 62, no. 10, page. 3441 - 3444, 2015-10

Article

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm NodeSCIESCOPUS

IEEE ELECTRON DEVICE LETTERS, vol. 36, no. 10, page. 994 - 996, 2015-10

Article

Learning-Based Ordering Characters on Ancient DocumentSCIESCOPUS

COMPUTATIONAL INTELLIGENCE AND NEUROSCIENCE, vol. 2022, 2022-11

Conference

Low Frequency Noise in SiC Double-Implant MOSFETs

제25회 한국반도체학술대회 (KCS 2018), 2018-02-07

Article

Low-Frequency Noise After Channel Soft Oxide Breakdown in HfLaSiO Gate DielectricSCIESCOPUS

IEEE ELECTRON DEVICE LETTERS, vol. 30, no. 5, page. 523 - 525, 2009-05

Conference

Low-Frequency Noise Behavior of La-Doped Hf-Based Dielectric nMOSFETs

Solid State Devices and Materials (SSDM2010), 2010-09-21

Article

Low-temperature performance of nanoscale MOSFET for deep-space RF applicationsSCIESCOPUS

IEEE ELECTRON DEVICE LETTERS, vol. 29, no. 7, page. 775 - 777, 2008-07

Conference

Low‐Frequency Noise Analysis in HfO2HfO2/SiON Gate Stack nMOSFETs with Different Interfacial Layer Thickness

ICPS 2010 (30th), 2010-07-25

Conference

Modeling and Analysis of the Parasitic Series Resistance in Raised Source/Drain FinFETs with Polygonal Shaped Epitaxy

IEEE SISPAD 2012, 2012-09-05

Article

Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact SchemesSCIESCOPUS

IEEE ACCESS, vol. 9, page. 138192 - 138199, 2021-10

Conference

Nanosheet Number and Width Optimization of Multi Stacked NanoSheet FET for 7-nm Node SoC Application

2018 International Conference on Solid State Devices and Materials (SSDM 2018), page. 877 - 878, 2018-09-12

Article

Nanowire Diameter Dependency of the Variability in n/p Silicon Nanowire FETs With Ultrashort Gate Length of 15 nmSCIESCOPUS

IEEE Transactions on Electron Devices, vol. 69, no. 12, page. 6529 - 6534, 2022-12

Article

Neural Approach for Modeling and Optimizing Si-MOSFET ManufacturingSCIESCOPUS

IEEE ACCESS, vol. 8, page. 159351 - 159370, 2020-08

Conference

Neural Network Based 14-nm Node Fully-Depleted FET Design for AC Applications of SoC and 3DIC

The 18th International Nanotech Symposium & Exhibition, 2020-07-01

Conference

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications

4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020, 2020-03-17

Article

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC ApplicationsSCIESCOPUS

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, vol. 8, page. 1272 - 1280, 2020-09

Conference

Neural Network-based Prediction for Cross-Temperature Induced VT Distribution Shift of 3D NAND flash memory

제 30회 한국반도체학술대회, 2023-02-15

Conference

New multi frequency capacitance extraction methodology for leaky MOS capacitor with High-K dielectric and metal gate

ISAGST 2008, 2008-09-29

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