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Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications SCIE SCOPUS

Title
Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications
Authors
Jeong, EYYoon, JSBaek, CKKim, YRHong, JHLee, JSBaek, RHJeong, YH
Date Issued
2015-10
Publisher
IEEE
Abstract
In this brief, we systematically investigated the effects of fin pitch (FP) and fin height (H-fin) on parasitic resistances and capacitances to achieve the best RC delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The RC delays were directly extracted from the fully calibrated technology computer aided design I-V/C-V simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the RC delay likewise increased due to greater C-gg. On the other hand, the RC delay mostly decreased due to greater ON-current as the H-fin increased. The RC delay with different power supply voltages (V-DD = 0.55 and 0.75 V) was also studied to see the effect of V-DD scaling. Finally, a selective deposition was suggested to improve the RC delay about 13%.
URI
https://oasis.postech.ac.kr/handle/2014.oak/37758
DOI
10.1109/TED.2015.2462760
ISSN
0018-9383
Article Type
Article
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 62, no. 10, page. 3441 - 3444, 2015-10
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정윤하JEONG, YOON HA
Dept of Electrical Enginrg
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