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Showing results 1 to 9 of 9
Conference
Analysis of Bottom Channel Effect in Silicon Nanowire FET based on Bulk-Silicon: Reduction of Parasitic Capacitance caused by SiGe layer

Solid State Devices and Materials (SSDM2011), 2011-09-28

Conference
Analysis of Parasitic Bottom Capacitance in n- and p-type Si-Nanowire Field Effect Transistors on Bulk

IEEE-NANO (2011), 2011-08-15

Conference
Comparative study on device performance of Junctionless double-gate MOSFET

대한전자공학회 하계학술대회 2010, 2010-06-16

Conference
Effects of fin height of tapered FinFETs on the sub-22nm System on Chip (SoC) application using TCAD simulation

IEEE VLSI-TSA (2013), 2013-04-22

Conference
Extraction of Series Resistance on Junctionless and Inversion-mode nanowire FET through the Method based on Y-function

IEEE DRC (2013), 2013-06-23

Conference
GIDL analysis of underlap double gate MOSFET with variable channel thickness and doping using quantum simulation

대한전자공학회 하계학술대회 2010, 2010-06-16

Thesis
Highly Efficient Silicon Solar Cell Based on Asymmetric Nanowire Structure

Thesis(Doctor), 2014

Conference
Investigation of GIDL Behavior in Si-Nanowire FET with Hot Carrier Stress

18th Korean Conference on Semiconductors (2011), 2011-02-16

Conference
Modeling and Analysis of the Parasitic Series Resistance in Raised Source/Drain FinFETs with Polygonal Shaped Epitaxy

IEEE SISPAD 2012, 2012-09-05

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