Open Access System for Information Sharing

OASIS Repository@POSTECHLIBRARY

Browsing by Author332

전체 가 나 다 라 마 바 사 아 자 차 카 타 파 하

All 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

or enter first few letters:

Sort by:
In order:
Results/Page
Authors/Record:

Showing results 93 to 112 of 148

Conference

Nanosheet Number and Width Optimization of Multi Stacked NanoSheet FET for 7-nm Node SoC Application

2018 International Conference on Solid State Devices and Materials (SSDM 2018), page. 877 - 878, 2018-09-12

Article

Nanowire Diameter Dependency of the Variability in n/p Silicon Nanowire FETs With Ultrashort Gate Length of 15 nmSCIESCOPUS

IEEE Transactions on Electron Devices, vol. 69, no. 12, page. 6529 - 6534, 2022-12

Article

Neural Approach for Modeling and Optimizing Si-MOSFET ManufacturingSCIESCOPUS

IEEE ACCESS, vol. 8, page. 159351 - 159370, 2020-08

Conference

Neural Network Based 14-nm Node Fully-Depleted FET Design for AC Applications of SoC and 3DIC

The 18th International Nanotech Symposium & Exhibition, 2020-07-01

Conference

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC applications

4th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2020, 2020-03-17

Article

Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC ApplicationsSCIESCOPUS

IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, vol. 8, page. 1272 - 1280, 2020-09

Conference

Neural Network-based Prediction for Cross-Temperature Induced VT Distribution Shift of 3D NAND flash memory

제 30회 한국반도체학술대회, 2023-02-15

Conference

New multi frequency capacitance extraction methodology for leaky MOS capacitor with High-K dielectric and metal gate

ISAGST 2008, 2008-09-29

Conference

Novel Extrinsic Series Resistance Extraction Methodology for Nanoscale MOSFETs

RFM 2008, 2008-12-02

Article

Novel High-Speed Ternary Logic Using Step-Shaped Threshold SwitchSCIESCOPUS

IEEE Electron Device Letters, vol. 44, no. 3, page. 368 - 371, 2023-03

Conference

Novel scheme to form non-uniform oxide in gate-all-around NCFETs for capacitance matching

제 30회 한국반도체학술대회, 2023-02-15

Conference

Observation of Mobility and Velocity as Channel Diameter Change in the Shrunk Lg = 18nm Silicon Nanowire MOSFETs

제1회 반도체공학회 학술대회, 2018-12-21

Conference

Observation of Mobility and Velocity Behaviors in Ultra Scaled Lg=15 nm Silicon Nanowire pMOSFETs with Different Channel Diameters

제26회 한국반도체학술대회 (KCS 2019), 2019-02-15

Article

Observation of mobility and velocity behaviors in ultra-scaled L-G=15 nm silicon nanowire field-effect transistors with different channel diametersSCIESCOPUS

SOLID-STATE ELECTRONICS, vol. 164, 2020-02

Conference

Optimal Energetic Trap Distribution of Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using Machine Learning Methodology

2021 International Conference on Solid State Devices and Materials, 2021-09-08

Conference

Optimization of Ge Mole Fraction in Sacrificial Layers for Sub-3-nm Node Silicon Nanosheet FETs

The 7th Electron Devices Technology and Manufacturing Conference (IEEE EDTM 2023), 2023-03-09

Conference

Optimized scalable I-V Modeling for 70nm Gate length Nano-CMOS using BSIM4

대한전자공학회 하계학술대회 2005, 2005-06-24

Conference

PBTI and HCI stress-induces trap generation in SiO2/HfO2 gate stack NMOSFETs and its impact on low frequency noise

ISAGST 2008, 2008-09-29

Conference

PEALD with Post-treatments for Interface Improvement of HfO2-based Metal-Insulator-Semiconductor Structures

제 29회 한국반도체학술대회, 2022-01-25

Conference

Physical DC and Thermal Noise Models of 18 nm DG Junctionless pMOSFETs

Solid State Devices and Materials (SSDM2014), 2014-09-08

1 2 3 4 5 6 7 8

OAK

개인정보처리방침 Personal Information Protection Policy

library@postech.ac.kr Tel: 054-279-2548

Open Access System for Information Sharing

Browsing by Author332

Browse