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PARK, HONG JUNE(박홍준) scopus

Department: Dept of Electrical Engineering(전자전기공학과)

Major(s): -

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Publication & Time Cited Count (For the Last 5 years)

Results 81-100 of 116 (Search time: 0.002 seconds).

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Date Issued : [2010 TO 2019]

Conference

An On-chip TSV Emulation Using Metal Bar Surrounded by Metal Ring to Develop Interface Circuits

International SoC Design Conference (ISOCC 2012), 2012-11-04

Conference

A 0.5V, 11.3-μW, 1-kS/s Resistive Sensor Interface Circuit with Correlated Double Sampling

IEEE Custom Integrated Circuits Conference, 2012-09-10

Conference

A 5Gb/s Single-Ended Parallel Receiver with Adaptive FEXT Cancellation

IEEE International Solid-State Circuits Conference(ISSCC), 2012-02-21

Conference

An 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface

IEEE International Solid-State Circuits Conference, page. 136 - 137, 2012-02-21

Conference

A 5Gb/s Single-Ended Parallel Receiver with Adaptive FEXT Cancellation

IEEE International Solid-State Circuits Conference, page. 140 - 141, 2012-02-21

Conference

Time-Interleaved Sample Clock Generator for Ultrasound Beamformer Application

International SoC Design Conference, page. 290 - 293, 2011-11-18

Conference

Time-Interleaved Sample Clock Generator for Ultrasound Beamformer Application

IEEE International SoC Design Conference(ISOCC2011), 2011-11-17

Conference

A Transmitter with Different Output Timing to Compensate for the Crosstalk-Induced Jitter of Coupled Microstrip Lines

IEIE & IEEE, ISOCC, 2011-11-17

Conference

A High-Gain Wide-Input-Range Time Amplifier with an Open-Loop Architecture and a Gain Equal to Current Bias Ratio

IEEE Asian Solid-State Circuits Conference, page. 325 - 328, 2011-11-16

Conference

Digital-Domain Calibration of Split-Capacitor DAC with no Extra Calibration DAC for a Differential-Type SAR ADC

IEEE Asian Solid-State Circuits Conference, page. 77 - 80, 2011-11-15

Conference

A High-Gain Wide-Input-Range Time Amplifier with an Open-Loop Architecture and a Gain Equal to Current Bias Ratio

IEEE Asian Solid-State Circuits Conference, 2011-11-14

Conference

Digital-Domain Calibration of Split-Capacitor DAC with no Extra Calibration DAC for a Differential-Type SAR ADC

IEEE Asian Solid-State Circuits Conference, 2011-11-14

Conference

A Fractional-N Frequency Divider for SSCG Using a Single Dual-Modulus Integer Divider and a Phase Interpolator

ISOCC, 2011-11-14

Conference

Phase-Blender-Based FIR Noise Filtering Techniques for ΔΣ Fractional-N PLL

IEEE International Midwest Symposium on Circuits and Systems, 2011-08-08

Conference

Phase-Blender-Based FIR Noise Filtering Techniques for ΔΣ Fractional-N PLL

MWSCAS 2011, 2011-08-07

Conference

Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits

ITC-CSCC, 2011-06-22

Conference

Reduction in the Peak Frequency Spectrum of Clock-Embedded Data-Signal for TFT-LCD Compared With the Regular-Clock and PRBS-Data Signals

International Technical Conference on Circuits/Systems, Computers and Communications, 2011-06-22

Conference

Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits

International Technical Conference on Circuits/Systems, Computers and Communications, 2011-06-22

Conference

Reduction in the Peak Frequency Spectrum of Clock-Embedded Data-Signal for TFT-LCD Compared With the Regular-Clock and PRBS-Data

International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC), 2011-06-19

Conference

A 2 GHz Fractional-N Digital PLL with lb Noise Shaping ΔΣ TDC

Symposium on VLSI Circuits, page. 116 - 117, 2011-06-16

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