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An 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface

Title
An 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface
Authors
심재윤박홍준김영식이선규
POSTECH Authors
심재윤박홍준
Date Issued
21-Feb-2012
Publisher
IEEE
URI
http://oasis.postech.ac.kr/handle/2014.oak/63112
Article Type
Conference
Citation
IEEE International Solid-State Circuits Conference, page. 136 - 137, 2012-02-21
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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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