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Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits
- Title
- Verilog Design of Asynchronous Clock Domain Crossing Techniques in High Speed Digital Transceiver Circuits
- Date Issued
- 2011-06-22
- Publisher
- International Technical Conference on Circuits/Systems, Computers and Communications
- Article Type
- Conference
- Citation
- International Technical Conference on Circuits/Systems, Computers and Communications, 2011-06-22
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Related Researcher
- 박홍준PARK, HONG JUNE
- Dept of Electrical Enginrg