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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 김영식 | - |
| dc.contributor.author | 박홍준 | - |
| dc.contributor.author | 이선규 | - |
| dc.contributor.author | 심재윤 | - |
| dc.date.accessioned | 2018-06-18T06:30:55Z | - |
| dc.date.available | 2018-06-18T06:30:55Z | - |
| dc.date.created | 2013-03-07 | - |
| dc.date.issued | 2012-02-21 | - |
| dc.identifier.uri | https://oasis.postech.ac.kr/handle/2014.oak/63112 | - |
| dc.publisher | IEEE | - |
| dc.relation.isPartOf | IEEE International Solid-State Circuits Conference | - |
| dc.relation.isPartOf | ISSCC | - |
| dc.title | An 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface | - |
| dc.type | Conference | - |
| dc.type.rims | CONF | - |
| dc.identifier.bibliographicCitation | IEEE International Solid-State Circuits Conference, pp.136 - 137 | - |
| dc.citation.conferenceDate | 2012-02-19 | - |
| dc.citation.conferencePlace | US | - |
| dc.citation.endPage | 137 | - |
| dc.citation.startPage | 136 | - |
| dc.citation.title | IEEE International Solid-State Circuits Conference | - |
| dc.contributor.affiliatedAuthor | 김영식 | - |
| dc.contributor.affiliatedAuthor | 박홍준 | - |
| dc.contributor.affiliatedAuthor | 이선규 | - |
| dc.contributor.affiliatedAuthor | 심재윤 | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- 박홍준PARK, HONG JUNE
- Dept of Electrical Enginrg