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dc.contributor.author심재윤ko
dc.contributor.author박홍준ko
dc.contributor.author김영식ko
dc.contributor.author이선규ko
dc.date.accessioned2018-06-18T06:30:55Z-
dc.date.available2018-06-18T06:30:55Z-
dc.date.created2013-03-07-
dc.date.issued2012-02-21-
dc.identifier.citationIEEE International Solid-State Circuits Conference, pp.136 - 137-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/63112-
dc.publisherIEEE-
dc.titleAn 8GB/s Quad-Skew-Cancelling Parallel Transceiver in 90nm CMOS for High-Speed DRAM Interface-
dc.typeConference-
dc.type.rimsCONF-
dc.contributor.localauthor심재윤-
dc.contributor.localauthor박홍준-
dc.citation.endPage137-
dc.citation.startPage136-
dc.citation.titleIEEE International Solid-State Circuits Conference-
dc.description.journalClass1-
dc.identifier.conferencecountryUS-

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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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