One-cycle correction of timing errors in pipelines with standard clocked elements
SCIE
SCOPUS
- Title
- One-cycle correction of timing errors in pipelines with standard clocked elements
- Authors
- Mukhopadhyay, S; Rao, RM; Kim, JJ; Chuang, CT
- Date Issued
- 2016-02
- Publisher
- IEEE
- Abstract
- One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. Because it prevents inputs arriving at a stage, which is stalled, it can also be used in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of 8%-12% with a target throughput of 0.9 instructions per cycle, and 15%-18% when the target is 0.8. © 1993-2012 IEEE.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/35850
- DOI
- 10.1109/TVLSI.2015.2409118
- ISSN
- 1063-8210
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 24, no. 2, page. 600 - 612, 2016-02
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