Post-silicon timing yield enhancement using dual-mode elements
SCIE
SCOPUS
- Title
- Post-silicon timing yield enhancement using dual-mode elements
- Authors
- Wook Kim; Hyoun Soo PARK; Kim, YH
- Date Issued
- 2009-07-30
- Publisher
- INST ENGINEERING TECHNOLOGY-IET
- Abstract
- A simple but effective technique for timing yield enhancement is presented. The proposed technique tunes circuit timing using dual-mode elements, which are special logic gates that can change delay leakage characteristics at the post-silicon level. In experiments using the ISCAS-85 benchmarks, the proposed technique reduced the timing failure rate by 59.52% on average.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/27818
- DOI
- 10.1049/EL.2009.1200
- ISSN
- 0013-5194
- Article Type
- Article
- Citation
- ELECTRONICS LETTERS, vol. 45, no. 16, page. 827 - 828, 2009-07-30
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- There are no files associated with this item.
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