Open Access System for Information Sharing

Login Library

 

Article
Cited 25 time in webofscience Cited 0 time in scopus
Metadata Downloads

A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs

Title
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs
Authors
Jeon, YJLee, JHLee, HCJin, KWMin, KSChung, JYPark, HJ
POSTECH Authors
Park, HJ
Date Issued
Jan-2004
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGI
Keywords
LOCKED LOOP; DIGITAL DLL; DRAM
URI
http://oasis.postech.ac.kr/handle/2014.oak/17647
DOI
10.1109/JSSC.2004.83
ISSN
0018-9200
Article Type
Article
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, no. 11, page. 2087 - 2092, 2004-01
Files in This Item:
There are no files associated with this item.

qr_code

  • mendeley

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

Related Researcher

Researcher

박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
Read more

Views & Downloads

Browse