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Design and analysis of a low-power ternary SRAM
- Title
- Design and analysis of a low-power ternary SRAM
- Date Issued
- 2021-05-23
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Abstract
- This paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89µA to 1.46µA. By connecting ternary inverters back-to-back, a tritstorage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.
- Article Type
- Conference
- Citation
- 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, 2021-05-23
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