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dc.contributor.authorChoi, Youngchang-
dc.contributor.authorKim, Sunmean-
dc.contributor.authorLee, Kyongsu-
dc.contributor.authorKang, Seokhyeong-
dc.date.accessioned2022-03-02T00:23:45Z-
dc.date.available2022-03-02T00:23:45Z-
dc.date.created2022-02-20-
dc.date.issued2021-05-23-
dc.identifier.urihttps://oasis.postech.ac.kr/handle/2014.oak/109690-
dc.description.abstractThis paper proposes the design of a ternary inverter that uses low current as input voltage is VDD/2. When the supply voltage is set to 1 V, current supplied by a voltage source as an input voltage VDD/2 is reduced by 22.75% from 1.89µA to 1.46µA. By connecting ternary inverters back-to-back, a tritstorage element is implemented as a ternary SRAM cell. This paper also presents the first verification of read/write schemes that consider noise margins.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.relation.isPartOf53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021-
dc.relation.isPartOfProceedings - IEEE International Symposium on Circuits and Systems-
dc.titleDesign and analysis of a low-power ternary SRAM-
dc.typeConference-
dc.type.rimsCONF-
dc.identifier.bibliographicCitation53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021-
dc.identifier.wosid000696765400205-
dc.citation.conferenceDate2021-05-22-
dc.citation.conferencePlaceKO-
dc.citation.title53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021-
dc.contributor.affiliatedAuthorKang, Seokhyeong-
dc.identifier.scopusid2-s2.0-85109030863-
dc.description.journalClass1-
dc.description.journalClass1-

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