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전체 가 나 다 라 마 바 사 아 자 차 카 타 파 하
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Showing results 1 to 20 of 453
Conference
1.2V 600-uW 단일루프 3차 구조의 Mobile Audio Sigma-Delta Modulator 설계

대한전자공학회, 2006-05-01

Conference
10 to 250MHz of Lock Range 0.4um Triple Well CMOS PLL

제 4회 반도체 학술대회, 1997-02-01

Conference
12bit CMOS A/D 변환기 칩의 설계, 제작 및 시험

제2회 반도체 학술 대회, 1995-02-01

Conference
12비트 125KS/s의 ADC를 내장한 모터 제어용 32비트 마이크로 콘트롤러

ASIC Design Workshop 2000, 2000-10-01

Conference
14bit self calibration CMOS A/D 변환기 칩의 설계, 제작 및 시험

제 2회 반도체 학술 대회, 1995-02-01

Article
5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge PumpSCIESCOPUS

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 58, no. 5, page. 269 - 273, 2011-05

Conference
55% Data Rate Increase of SSTL DRAM Interface Channels by Eliminating Crosstalk-Induced Jitter

2008 대한전자공학회 추계학술대회, 2009-11-28

Conference
55% Data Rate Increase of SSTL DRAM Interface Channels by Eliminating Crosstalk-Induced Jitter

대한전자공학회 추계종합학술대회, page. 21 - 22, 2009-11-28

Conference
-60dB THD, 32ohm load, 0.7Vrms 출력의 저전력 CMOS class AB Stereo Audio Amplifier 설계

대한전자공학회 2005 추계학술대회, page. 905 - 908, 2005-11-01

Conference
6bit 1.1GS/s CMOS Flash ADC

IEEK SOC Design Conference, page. 191 - 194, 2003-11-01

Conference
8-GS/s 4-비트 CMOS 타임 인터리브 플래쉬 아날로그/디지털 변환기

한국군사과학기술학회 종합학술대회, page. 405 - 408, 2003-08-01

Conference
840 Mb/s CMOS demultiplexed equalizing transceiver for DRAM-to processor communication

Symposium on VLSI Circuits, page. 23 - 24, 1999-06-17

Conference
840 Mb/s CMOS Demultiplexed Equalizing Transceiver for DRAM-to Processor Communication

Symp.On VLSI Circuits Digest of Technical Papers, page. 23 - 24, 1999-06-01

Article
A 0.0043-mm(2) 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDCSCIESCOPUS

IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 54, no. 1, page. 99 - 108, 2019-01

Conference
A 0.0047mm2 Highly Synthesizable TDC and DCO-less Fractional-NPLL with a Seamless Lock - Range off RER to 1GHz

IEEE International Solid-State Circuits Conference (ISSCC), 2017-02-07

Conference
A 0.0047mm2 Highly Synthesizable TDC- and DCO-Less Fractional-N PLL with a Seamless Lock Range of fREF to 1GHz

IEEE International Solid-State Circuits Conference, 2017-02-05

Conference
A 0.1-fref BW 1GHz Fractional-N PLL with FIR-Embedded Phase-Interpolator-Based Noise Filtering

IEEE International Solid-State Circuits Conference, page. 94 - 95, 2011-02-21

Conference
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering

ISSCC 2011, 2011-02-20

Article
A 0.12GHz-1.4GHz DLL-based clock generator with a multiplied 4-phase clock using a 0.18um CMOS process

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol. 6, no. 4, page. 264 - 269, 2006-12

Conference
A 0.12GHz-1.4GHz DLL-based clock generator with a multiplied 4-phase clock using a 0.18um CMOS process

International SoC Design Conference, page. 241 - 244, 2006-10-01

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