A 0.0043-mm(2) 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC
SCIE
SCOPUS
- Title
- A 0.0043-mm(2) 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC
- Authors
- Lee, Minseob; Kim, Shinwoong; Park, Hong-June; Sim, Jae-Yoon
- Date Issued
- 2019-01
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- This paper presents a synthesized fractional-N digital phase-locked loop (PLL) with a speculative dual-referenced interpolating time-to-digital converter (DI-TDC). The DI-TDC measures a fractional phase by referencing two adjacent quadrant boundaries which are given by a four-phase digitally controlled oscillator (DCO). It achieves a robust gain matching to the first order without need of any calibration. By predicting a time region of interest for the next TDC conversion, the power and area overheads for DI-TDC is minimized. Except for DCO and a reference delay chain, the PLL is implemented with register-transfer level (RTL) behavioral descriptions followed by an automated synthesis. It is fabricated in 28-nm CMOS with an active area of 0.0043 mm(2). The PLL shows a wide frequency lock range operating at a supply voltage from 0.3 to 1.2 V, achieving a stable figure-of-merit of better than -220 dB for a supply voltage above 0.6 V.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/99938
- DOI
- 10.1109/JSSC.2018.2876464
- ISSN
- 0018-9200
- Article Type
- Article
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 54, no. 1, page. 99 - 108, 2019-01
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