5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump

Abstract

A 5-Gb/s current-mode peak detector is proposed using a V-I converter, a current comparator, and a charge pump with three states (i.e., UP, DN, and HOLD). It eliminates the problem that a voltage error increases with an input data rate in a conventional peak detector circuit. In this brief, the voltage error between the measured input and output peak voltages is smaller than 5% for a pseudo-random binary sequence signal at a data rate up to 5 Gb/s, with an input voltage swing up to +/- 500 mV and an input common-mode voltage of 0.9 V. A chip fabricated in a 0.18-mu m process gives the power consumption of 2.7 mW at a voltage supply of 1.8 V and a chip area of 150 mu m x 120 mu m.