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PARK, HONG JUNE(박홍준) scopus
Department
Dept of Electrical Engineering(전자전기공학과)
Major(s)
-

Co-researchers

    Keyword

    Publication & Time Cited Count (For the Last 5 years)

    Results 1-20 of 36 (Search time: 0.002 seconds).
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    Date Issued : [2000 TO 2009]
    Conference
    An Analytic Decision Method for the Feed-forward Equalizer Tap-Coefficients at Transmitter

    International SoC Design Conference, page. 400 - 403, 2009-11-24

    Conference
    An Analytic Decision Method for the Feed-forward Equalizer Tap-Coefficients at Transmitter

    International SoC Design Conference, 2009-11-24

    Conference
    A 5-7 Gbps Peak Detector for Serial-Link

    International SoC Design Conference, 2009-11-23

    Conference
    A 5-7 Gbps Peak Detector for Serial-Link

    International SoC Design Conference, 2009-11-23

    Conference
    A 1.3uW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18um CMOS

    Symposium on VSLI Circuits, 2009-06-18

    Conference
    A 1.3uW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18um CMOS

    Symp. on VLSI Circuits, 2009-04-27

    Conference
    A 650Mb/s-to-8Gb/s Referenceless CDR Circuit with Automatic Acquisition of Data Rate

    IEEE International Solid-State Circuits Conference, 2009-02-10

    Conference
    A 1V 2.8Gbps 0.18µm CMOS Inverter-Based Digital Cifferential Transmitter with Calibrations of Termination and Misnatch

    International SoC Conference, 2008-11-24

    Conference
    A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization

    International SoC Design Conference, 2008-11-24

    Conference
    A 1V 2.8Gbps 0.18µm CMOS Inverter-Based Digital Cifferential Transmitter with Calibrations of Termination and Misnatch

    International SoC Conference, 2008-11-24

    Conference
    A Design Guide for 3-stage CMOS Nested Gm-C Operational Amplifier with Area or Current Minimization

    International SoC Design Conference (ISOCC), 2008-11-24

    Conference
    A Transister-Based Background Self-Calibration for Reducing PVT Sensitivity with Design Example of an Adaptive Bandwidth PLL

    IEEE Asian Solid-State Circuits Conference, 2008-11-04

    Conference
    A 4Gbps 3-bit parallel Transmitter with the Crosstalk-Induced Jitter Compensation using TX Data Timing Control

    IEEE Asian Solid-State Circuits Conference, 2008-11-04

    Conference
    A 8 GByte/s Transceiver with Current-Balanced Pseudo-Differential Signaling for Memory Interface

    IEEE Asian Solid-State Circuits Conference, 2008-11-04

    Conference
    A Transister-Based Background Self-Calibration for Reducing PVT Sensitivity with Design Example of an Adaptive Bandwidth PLL

    IEEE Asian Solod-State Circuits Conference, 2008-11-03

    Conference
    A Low-Voltage OP Amp with Digitally Controlled Algorithmic Approximation

    IEEE Custom Integrated Circuits Conference, 2008-09-21

    Conference
    A Low-Voltage OP Amp with Digitally Controlled Algorithmic Approximation

    IEEE Custom Integrated Circuits Conference, 2008-09-03

    Conference
    A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

    ISSCC2008, 2008-02-04

    Conference
    A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration

    IEEE International Solid-State Circuits Conference, 2008-02-03

    Conference
    A 5Gb/s 16-bit Transmitter with Segmented Group-Inversion Encoding

    International SoC Design Conference, 2007-10-15

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