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A 8 GByte/s Transceiver with Current-Balanced Pseudo-Differential Signaling for Memory Interface

Title
A 8 GByte/s Transceiver with Current-Balanced Pseudo-Differential Signaling for Memory Interface
Authors
심재윤이선규지동우서윤재박홍준
POSTECH Authors
심재윤박홍준
Date Issued
4-Nov-2008
Publisher
IEEE
URI
http://oasis.postech.ac.kr/handle/2014.oak/51122
Article Type
Conference
Citation
IEEE Asian Solid-State Circuits Conference, 2008-11-04
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박홍준PARK, HONG JUNE
Dept of Electrical Enginrg
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