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Cited 3 time in webofscience Cited 8 time in scopus
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A Case for Memory-Centric HPC System Architecture for Training Deep Neural Networks

Title
A Case for Memory-Centric HPC System Architecture for Training Deep Neural Networks
Authors
Kwon, YoungeunRhu, Minsoo
Date Issued
Jul-2018
Publisher
IEEE COMPUTER SOC
Abstract
As the models and the datasets to train deep learning (DL) models scale, system architects are faced with new challenges, one of which is the memory capacity bottleneck, where the limited physical memory inside the accelerator device constrains the algorithm that can be studied. We propose a memory-centric deep learning system that can transparently expand the memory capacity accessible to the accelerators while also providing fast inter-device communication for parallel training. Our proposal aggregates a pool of memory modules locally within the device-side interconnect, which are decoupled from the host interface and function as a vehicle for transparent memory capacity expansion. Compared to conventional systems, our proposal achieves an average 2: 1 x speedup on eight DL applications and increases the system-wide memory capacity to tens of TBs.
URI
http://oasis.postech.ac.kr/handle/2014.oak/99268
ISSN
1556-6056
Article Type
Article
Citation
IEEE COMPUTER ARCHITECTURE LETTERS, vol. 17, no. 2, page. 134 - 138, 2018-07
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유민수RHU, MINSOO
Dept of Computer Science & Enginrg
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