Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC

Abstract

Among power dissipation components, leakage power has become more dominant with each successive technology node. Power-gating techniques have been widely used to reduce the standby leakage energy. In this work, we investigate a power-gating strategy for through-silicon via (TSV)-based 3D IC stacking structures. Power-gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC to perform power-gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power-gating strategy that optimizes the in-rush current profile, subject to the voltage-drop constraints. Our power-gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating is analyzed in terms of the wake-up time reduction. We achieve an average wake-up time reduction of 43% for all cases with our adaptive power-gating method that exploits location (or layer) information regarding the aggressors in a 3D IC. A tapered TSV architecture based on the layer dependency has been analyzed; it exhibits up to 18% wake-up time reduction compared to that of circuits with uniform TSVs.