Scalable on-chip network in power constrained manycore processors
- Title
- Scalable on-chip network in power constrained manycore processors
- Authors
- KIM, HANJOON; KIM, GWANGSUN; KIM, JOHN
- Date Issued
- 2012-06-04
- Publisher
- IEEE Computer Society
- Abstract
- While much research has been done using 2D mesh network as a baseline on-chip network topology, recent multi-core chips from vendors leverage a ring topology. In this work, we re-visit the topology comparison in on-chip networks and model the impact of on-chip network on overall performance while holding the entire chip power constant. We vary the amount of power allocated to the on-chip network and evaluate its impact on overall performance to determine a balanced system design. We show how the ring topology is efficient in current technology at 45nm but the scalability is limited as technology continues to scale and show how a simple hierarchical ring approach can provide a scalable solution.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/94460
- Article Type
- Conference
- Citation
- 3rd International Green Computing Conference, 2012-06-04
- Files in This Item:
- There are no files associated with this item.
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