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Studies on the Interface Tuning of Organic Field-Effect Transistors for Improving Operational Reliability

Studies on the Interface Tuning of Organic Field-Effect Transistors for Improving Operational Reliability
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Organic field-effect transistors (OFETs) are one of the promising devices for application in next-generation flexible and wearable electronics such as flexible displays, radio-frequency identification tags, and chemical or biological sensors. The considerable progress in organic semiconductor material syntheses have enabled the remarkable development of organic semiconductors based OFETs. Solution and/or printing procedures allow the direct patterning of organic materials for fabricating OFETs. However, the operational instability of OFETs under sustained bias stress is prerequisite to commercialization. The operational stability can be described as gate-bias stress effect, which leads the reduction in drain current and the shift of threshold voltage under a sustained bias stress. The gate-bias stress instability is mainly caused by the trapping of mobile carriers in localized trap states of the organic semiconductor layer, the dielectric layer, or at the organic semiconductor and dielectric interface. Basics of OFETs about operation, charge transport/injection, and operational stability were introduced in Chapter 1. In Chapter 2, 3, and 4, the gate-bias stress effect of top-contact OFETs was improved by controlling surface properties of the dielectric layer and the correlation between dielectric surface and the operational reliability of OFETs were investigated. The work function of source/drain electrodes was tuned by surface treatments and its effect on charge injection and operational stability of OFETs were studied in Chapter 5 and 6. In Chapter 2, I report the polarity effect of dielectric surface on the stability of triethylsilyethynyl anthradithiophene (TES-ADT) based OFETs. The operational stability of OFETs was significantly affected by dielectric surface polarity which was controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH3)2Cl) to 300-nm-thick SiO2 dielectrics. On the untreated and treated SiO2 dielectrics, solvent-vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The electrical performance and gate-bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with decreasing dielectric surface polarity. Among dielectrics with similar capacitances (10.5 – 11 nFcm-2) and surface roughnesses (0.40 – 0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and the charge-carrier mobility ~1.32 cm2V–1s–1, on-off current ratio > 106, threshold voltage ~ 0 V, and long-term operation stability under negative bias stress. Highly stable OFETs using fluorine-rich polymer dielectric (cross-linked poly(3-(hexafluoro-2-hydroxyl) propyl) styrene (PFS)) were demonstrated in Chapter 3. PFS showed the excellent electrical stability, good adhesive surface properties, and the good wettability on deposited solution-processed materials. Solution-processed triethylsilylethynyl anthradithiophene (TES-ADT) could be deposited onto the cross-linked PFS dielectric to yield highly ordered crystalline structures. The field-effect mobility was as high as 0.56 cm2V–1s–1, and negligible hysteresis was observed in OFETs. The threshold voltage, ON/OFF ratio, and subthreshold slope were – 0.043 V, ~ 107, and – 0.3 V/decade, respectively. OFETs exhibited the excellent device reliability under gate-bias stress conditions due to the presence of highly stable fluorine groups in the cross-linked PFS dielectric. I report that the correlation between dielectric surface and operational reliability of OFETs in Chapter 4. The bias stress stability of OFETs with methoxy-, methyl-, and fluoro-functional styrene treated dielectric surfaces was investigated. Based on the comprehensive study about the trap that cause gate-bias stress instability, I could conclude that the device instability behavior should be intimately related to the charge transfer from semiconductor to dielectric layer under gate-bias stressing. Since the charge transfer phenomena should be directly proportional to the degree of overlap between semiconductor’s and dielectric’s highest occupied molecular orbital (HOMO), the energetic difference between two HOMOs acts as a “energetic barrier” to the charge transfer taken place in the semiconductor/dielectric interface. Based on this result, I could demonstrate highly stable OFET which has dielectric surface with high energetic barrier by adopting the fluorinated functional dielectric. I believe these results will suggest fundamental origin for the gate-bias stress instability and be give standard for organic electronics community. The use of polytetrafluoroethylene (PTFE) contained (poly(3,4-ethylenedioxythiophene):polystyrene sulfonate) (PEDOT:PSS) as hole injection layer of source/drain electrodes in highly stable pentacene-based bottom-contact OFETs was described in Chapter 5. The (PEDOT:PSS):PTFE layer was deposited on the Au layer by spin coating a mixture solution. The work function of the electrode increased from 4.84 to 5.21 eV as the PTFE concentration increased, accompanied by an interface dipole at the electrode surface. The optimized (PEDOT:PSS):PTFE (0.95:0.05)-treated electrode significantly reduced the charge injection barrier at the electrode/semiconductor interface to achieve efficient charge transfer in OFETs. Bottom-contact OFETs prepared with optimized (PEDOT:PSS):PTFE-treated source/drain electrodes had a field-effect mobility of 0.16 cm2V–1s–1, which exceeded that of PEDOT:PSS-treated source/drain electrodes (0.073 cm2V–1s–1). The operational stability of optimized device was remarkable under gate-bias stress. In Chapter 6, I report excellent stable OFETs by the introduction of fluorinated polymer (Nafion) to poly(3,4-ethylenedioxythiophene):poly(4-styrenesulfonate) (PEDOT:PSS) as source/drain electrodes. The PEDOT:PSS/Nafion as source/drain electrodes was formed by electrohydrodynamic (EHD) printing. The surface property of electrode could be controlled by varying Nafion ratios due to vertically phase separation of the PEDOT:PSS/Nafion. The PEDOT:PSS with Nafion exhibited high work function, thereby lowering hole injection barrier that leaded remarkable charge injection from the electrode to the semiconductor. The lower hole injection barrier disturbed the trapping and promoted the de-trapping of holes at the electrode and semiconductor interface. As a result, a mobility of OFETs with PEDOT:PSS/Nafion electrode (0.13 cm2V–1s–1) was approximately four orders of magnitude higher than that of PEDOT:PSS electrode device (2.19×10-4 cm2V–1s–1), and the operational stability of the device was significantly improved.
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