An Automatic ReRAM SPICE Model Generation Methodology for ReRAM-Circuit Co-Simulation

Abstract

This paper presents an automatic ReRAM SPICE model generation methodology which enables true ReRAM-circuit co-simulation in standard SPICE. In our method, a model generation tool automatically produces SPICE models of various ReRAM devices and selectors from the measured I-V data including newly measured ReRAM's SET behavior in our proposed experiment. The generated models are compatible with standard SPICE and can describe diverse ReRAM behaviors including nonlinear I-V characteristic, I-V relationship during SET, and dependency of I-V curve on SET current. Because describing these behaviors in standard SPICE has been the critical obstacle to simulate ReRAMs and circuits together, especially in multi-level cell simulation, our method can be a key enabler of ReRAM-circuit co-simulation. To verify our method, SPICE models for diverse ReRAMs were generated and simulated. The results show that our model can accurately describe the original data. To demonstrate the usefulness of our method, we also simulated and analyzed example ReRAM circuits such as 1R and 1S1R arrays and a complex CMOS sensing circuit for ReRAM. These simulations and analyses show that our method enables quantitative ReRAM analyses such as trade-off analyses for reading margin and sensing delay.