System Level Solutions for Memory Reliability

Abstract

Reliability of a memory subsystem is one of the most important feature to computer system stability, since memory errors can make whole system failures. Past few years, as VLSI technology node scales down, various factors which are degrading the reliability of memory operation have been appeared. This dissertation addresses memory errors in SRAM and DRAM, which are commonly used to on-chip cache memory and main memory, respectively. In the SRAM-based cache memory, SRAMs limit the lowest supply voltage in processor since they suffer from process variation-induced bit errors at a low supply voltage. Therefore, on-chip SRAM-based caches are the practical bottleneck to reducing supply voltage which is one of the key parameters for lowering energy consumption. In order to address this problem, a novel cache architecture is proposed to resolve the performance degradation at a low supply voltage which is caused by cache misses in accesses to faulty resources. The proposed solution utilizes cache access locality and error-free resources in a cost-effective manner. First, cache lines are classified into fully and partially accessed groups and apply appropriate methods to each group. For the partially accessed group, memory access behavior and error locations are matched with intra-cache line word-level remapping. In order to reduce the area overhead used to store the cache access information history, an access pattern-learning line-fill buffer is adopted. For the fully accessed group, the proposed solution utilizes error-free assist functions such as a line-fill buffer and victim cache with no process variation-induced error at the target minimum supply voltage. The solution also present an error-aware prefetch method that allows it to utilize the error-free victim cache to achieve a further reduction in cache misses due to faulty resources. In the DRAM-based main memory, bit errors are expected to increase at a rapid pace as DRAM approaches its scaling limit. At high bit error rates, the conventional strong error correction mechanisms are not sufficient for reliable computing. Therefore, a novel architectural solution for DRAM-based main memory is proposed to provide better reliability, at low cost, than conventional solutions under scaling-induced DRAM cell faults. By utilizing modification of the existing two-dimensional error correction scheme and error correcting table scheme, multi-bit errors can be tolerate in this solution. The solution has two implementations, i.e. in-DRAM and SRAM parity methods, depending on whether DRAM capacity can be sacrificed or not for parity storage. In both cases, in order to avoid the performance overhead incurred by additional data read operations (called pre-data reads) for parity calculations, partial parity and a last-level cache (LLC) architecture that manages partial parity are utilized. When parity bits can be stored in main memory (referred to as in-DRAM parity method), in order to hide the latency of additional parity accesses to DRAM, it is possible to exploit the slack between an eviction from the LLC and the associated initial write to the LLC, thereby hiding the additional latency of accessing parity in DRAM. Since the proposed solutions are applied to different scopes in memory subsystem, they can be jointly utilized by same memory subsystem. Therefore, jointly applying both of the solutions, reliability of the system can be improved for various operating condition such as low supply voltage condition and defective DRAM-based main memory.