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HfSiON/SiO2 nMOSFET에 발생하는 Positive Bias Temperature Instability 열화의 전압 의존성 평가

Title
HfSiON/SiO2 nMOSFET에 발생하는 Positive Bias Temperature Instability 열화의 전압 의존성 평가
Authors
김철규
Date Issued
2015
Publisher
포항공과대학교
Abstract
This thesis investigates a voltage-dependent degradation of HfSiON/SiO2 nMOSFETs under conditions of positive bias temperature instability (PBTI), proposes a PBTI degradation models that can predict device lifetime accurately using data from acceleration tests, and examines the effect of fast transient charge relaxation from pre-existing defects to PBTI degradation. When a thin HfSiON layer was used for gate dielectric of HfSiON/SiO2 nMOSFET, the PBTI stress generated shallow traps in HfSiON and the exponent n of power-law ΔVth∝tn for threshold-voltage shift ΔVth increased exponentially with an increase of PBTI gate stress voltage Vg,str. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime tL = 1.64E10 s, which agreed well with the tL = 1.92E10 s measured at low gate stress voltage, whereas the conventional model overestimates tL by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating tL of high-k nMOSFETs. When a thick HfSiON layer was used for gate dielectric of HfSiON/SiO2 nMOSFET, a secondary-hole trapping occurred in the bulk dielectric due to hole injection at the anode after electron trapping in the initial bulk trap. This secondary-hole trapping causes a decrease in the time exponent n of the power law as Vg,str increases. This dependency of n on Vg,str results in overestimation of tL when it was estimated using the conventional method which assumes a constant value of n. An empirical model that considers the effect of Vg,str on n is proposed; this model predicted operational tL = 2.6E5 s, which agreed well with experimentally-measured tL = 3.9E5 s. The effect of fast transient electron de-trapping from pre-existing defects of HfSiON layer is also investigated. When the duration tm for Vth-sensing period is long, the fast electron de-trapping at pre-exsiting defect of HfSiON layer increased. So, the difference between the ΔVths measured at different tm appeared only at the initial ΔVths. This fast electron de-trapping for PBTI degradation was included in the proposed charge relaxation model. This model is useful for predicting the results of slow measurement using the results of fast measurement. The fast trapped oxide charge density estimated using this model was 9.36E12 cm-2 at Vg,str = 2.5 V. The experimental results of this thesis show that the PBTI degradation of HfSiON/SiO2 nMOSFET strongly depends on Vg,str, thickness of HfSiON layer, and duration of Vth-sensing measurement. The proposed model includes all these non-ideal effects. So, the PBTI degradation of HfSiON/SiO2 nMOSFETs can be estimated accurately by applying the proposed model to experimentally measured data.
URI
http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001911088
http://oasis.postech.ac.kr/handle/2014.oak/93170
Article Type
Thesis
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