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다양한 VLSI 설계 단계에서의 확률 통계적인 Timing 해석의 유효성
- Title
- 다양한 VLSI 설계 단계에서의 확률 통계적인 Timing 해석의 유효성
- Authors
- 양형균
- Date Issued
- 2009
- Publisher
- 포항공과대학교
- URI
- http://postech.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000001909790
https://oasis.postech.ac.kr/handle/2014.oak/9033
- Article Type
- Thesis
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