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Verilog Synthesis of USB 2.0 Full-speed Device PHY IP
- Title
- Verilog Synthesis of USB 2.0 Full-speed Device PHY IP
- Date Issued
- 2013-11-19
- Publisher
- IEEE
- Article Type
- Conference
- Citation
- International SoC Design Conference, 2013-11-19
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Related Researcher
- 김병섭KIM, BYUNGSUB
- Dept of Electrical Enginrg