Impact of High-ĸ Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node
- Title
- Impact of High-ĸ Spacers on Parasitic Effects Considering DC/AC Performance Optimization in Si-Nanowire FETs for sub 10 nm Technology Node
- Authors
- 정윤하; 홍재호
- Date Issued
- 2014-09-09
- Publisher
- Japanese Journal of Applied Physics
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/68786
- Article Type
- Conference
- Citation
- 2014 International Conference on Solid State Devices and Materials, 2014-09-09
- Files in This Item:
- There are no files associated with this item.
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