Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering
SCIE
SCOPUS
- Title
- Demonstration of Low Power 3-bit Multilevel Cell Characteristics in a TaOx-Based RRAM by Stack Engineering
- Authors
- Prakash, A; Park, Jaesung; Song, Jeonghwan; Woo, Jiyong; Cha, Eui-Jun; Hwang, H
- Date Issued
- 2015-01
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Abstract
- Multilevel cell (MLC) storage technology is attractive in achieving ultrahigh density memory with low cost. In this letter, we have demonstrated 3-bit per cell storage characteristics in a TaOx-based RRAM. By analyzing the key requirements for MLC operation mainly the switching uniformity and stability of resistance levels, an engineered stack based on thermodynamics in top electrode/(vacancy reservoir/defect control layer)/switching layer/bottom electrode structure was designed. In the optimized stack with similar to 10-nm Ta layer incorporated at W/TaOx interface, seven low resistance state levels with same high resistance state were obtained by controlling the switching current down from 30 mu A enabling low power 3-bit storage in contrast to the control device which shows 2-bit MLC with resistance saturation. The improved switching and MLC behavior is attributed to the minimized stochastic nature of set/reset operations due to filament confinement by favorable electric field generation and formation of thin but highly conductive filament which is confirmed electrically.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/50131
- DOI
- 10.1109/LED.2014.2375200
- ISSN
- 0741-3106
- Article Type
- Article
- Citation
- IEEE ELECTRON DEVICE LETTERS, vol. 36, no. 1, page. 32 - 34, 2015-01
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