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Effects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology
- Title
- Effects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology
- Date Issued
- 2013-06-10
- Publisher
- IEEE
- Article Type
- Conference
- Citation
- International Symposium on VLSI Technology (VLSI2013), 2013-06-10
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Related Researcher
- 백록현BAEK, ROCK HYUN
- Dept of Electrical Enginrg