Effects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology
- Title
- Effects of Layout and Process Parameters on Device/Circuit Performance and Variability for 10nm Node FinFET Technology
- Authors
- 백록현; 강창용; 손창우; C.Hobbs; P.Kirsch; R.Jammy
- Date Issued
- 2013-06-10
- Publisher
- IEEE
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/49472
- Article Type
- Conference
- Citation
- International Symposium on VLSI Technology (VLSI2013), 2013-06-10
- Files in This Item:
- There are no files associated with this item.
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