Optimization of cross-linked poly(4-vinylphenol) gate dielectric for low-temperature vertically stacked organic thin-film transistors and logic circuits on a flexible substrate

Abstract

A polymer gate dielectric is one of the key elements of high-performance solution-processed organic thin-film transistors (OTFTs) for low-cost, large-area, flexible electronic applications. For the past decade a poly(4-vinylphenol) (PVP) dielectric cross-linked with poly(melamine-co-formaldehyde) (PMF) has been widely used due to its low leakage current, high capacitance, and high chemical compatibility in OTFTs. However, the cross-linked PVP (cPVP) dielectric has been compatible only with suitably engineered expensive plastic substrates due to its high curing temperature (typically >150 °C). In this study, we sought to find the optimum PVP:PMF weight ratio to fabricate low-temperature, solution-processed OTFTs on polyethylene naphthalate. We investigated the influence of different cPVP conditions such as PVP:PMF weight ratio (0.2:1 to 5:1) and annealing temperature (100 to 200 °C) on the performances of 6,13-bis(triisopropylsilylethynyl):polystyrene blend OTFTs. We found that the OTFT using the PVP:PMF with the weight ratio of 1:2 showed negligible gate-bias stress, low gate leakage current, and strong chemical resistance in common solvents, even though the dielectric film was annealed at 100 °C. Fourier transform infrared spectroscopy measurements provided the evidence that device performances were influenced by the weight ratio and annealing temperature of the cPVP dielectric due to the presence of free and hydrogen-bonded hydroxyl groups. Finally, we demonstrated vertically integrated OTFTs with the optimized cPVP dielectric to form three-dimensional universal logic NAND gate. This work shows that cPVP is a suitable dielectric material to fabricate flexible electronic devices and circuits on inexpensive plastic substrates with high transistor density and high yield.