Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory

Abstract

The effects of single grain boundary (SGB) position and stored electron charges in an adjacent cell in silicon–oxide–nitride–oxide–silicon (SONOS) structures on the variations of threshold voltage (V th) were investigated using technology computer-aided design (TCAD) simulation. As the bit line voltage increases, the SGB position causing the maximum V th variation was shifted from the center to the source side in the channel, owing to the drain-induced grain barrier lowering effect. When the SGB is located in the spacer region, the potential interaction from both the SGB and the stored electron charges in the adjacent cell becomes significant and thus resulting in larger V th variation. In contrast, when the SGB is located at the center of the channel, the peak position of potential barrier is shifted to the center, so that the influence of the adjacent cell is diminished. As the gate length is scaled down to 20 nm, the influence of stored charges in adjacent cells becomes significant, resulting in larger V th variations.