A two-step-recess process based on atomic-layer etching for high-performance In(0.52)Al(0.48)As/In(0-53)Ga(0.47)As p-HEMTs
SCIE
SCOPUS
- Title
- A two-step-recess process based on atomic-layer etching for high-performance In(0.52)Al(0.48)As/In(0-53)Ga(0.47)As p-HEMTs
- Authors
- Kim, TW; Kim, DH; Park, SD; Shin, SH; Jo, SJ; Song, HJ; Park, YM; Bae, JO; Kim, YW; Yeom, GY; Jang, JH; Song, JI
- Date Issued
- 2008-07
- Publisher
- IEEE Transactions on Electron Devices
- Abstract
- We investigated 60-nm In0.52Al0.48As/In0.53Ga0.47 As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 angstrom/cycle for an InP etch stop layer, an, excellent InP etch selectivity of 70 against an In0.52Al0.48As barrier layer, and an rms surface-roughness value of 1.37 angstrom for the exposed In0.52Al0.48As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs produced improved device parameters, including transconductance (G(M)), cutoff frequencies (f(T)), and electron saturation velocity (V-sat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In0.52Al0.48As/In0.53Ga0.47As p-HEMTs fabricated by using the ALET technology exhibited G(M),(Max) = 1.17 S/mm, f(T) = 398 GHz, and V-sat = 2.5 x 10(7) cm/s.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/37365
- DOI
- 10.1109/TED.2008.923522
- ISSN
- 0018-9383
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 55, no. 7, page. 1577 - 1584, 2008-07
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