A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization
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- Title
- A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization
- Authors
- Choi, S; Son, H; Shin, J; Lee, SH; Kim, Byungsub; Park, HJ; Sim, JY
- Date Issued
- 2016-02
- Publisher
- IEEE
- Abstract
- This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problemwith a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of 10(-12). The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s.
- Keywords
- Adaptive equalization; asynchronous sampling; clock and data recovery (CDR); continuous time linear equalizer (CTLE); frequency acquisition; reference-less CDR; rotational frequency detector (RFD)
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/37181
- DOI
- 10.1109/TCSI.2015.2512713
- ISSN
- 1549-8328
- Article Type
- Article
- Citation
- IEEE Transactions on Circuits and SYSTEMS—I: Regular Papers, vol. 63, no. 2, page. 276 - 2871549-83, 2016-02
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