A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface
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- Title
- A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface
- Authors
- Soo-Min Lee; Ji-Hoon Lim; Il-Min Yi; Young-Jae Jang; Jung, HK; Kyunghoon Kim; Daehan Kwon; Kim, B; Sim, JY; Park, HJ
- Date Issued
- 2016-08
- Publisher
- IEEE
- Abstract
- A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of similar to 10 dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s.
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/37137
- DOI
- 10.1109/JSSC.2016.2559512
- ISSN
- 0018-9200
- Article Type
- Article
- Citation
- IEEE Journal of Solid-State Circuits, vol. 51, no. 8, page. 1890 - 1901, 2016-08
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