Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control

Abstract

Highly linear and efficient CMOS cascode power amplifiers (PAs) are developed for handset applications. The linearity of the PAs is improved using adaptive bias circuits at the gates of the common-source (CS) and the common-gate (CG) stages. The memory effects that are generated by the bias circuits are reduced using second harmonic control circuits at the source of the CS and the gate of the CG stages. The proposed PA, including the integrated bias circuits, is fabricated using a 0.18 - mu mRF CMOS technology. The adaptive gate bias circuits improve the linearity and efficiency significantly. The measurement results show that the side-band asymmetry is less than 1.5 dB and the peak average power is improved by 1.2 dB within the linearity specification for a 16-QAM 7.5 dB PAPR LTE signal. The bias circuits improve the linearity of the PA within the specification without using digital pre-distortions. The CMOS PA delivers a power-added efficiency (PAE) of 41.0%, an error vector magnitude (EVM) of 4.6%, and an average output power of 27.8 dBm under an ACLR(E-UTRA) of -31.0 dBc for a 10-MHz bandwidth signal at 1.85-GHz carrier frequency.