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Cited 13 time in webofscience Cited 13 time in scopus
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dc.contributor.authorBae, SJko
dc.contributor.authorChi, HJko
dc.contributor.authorSohn, YSko
dc.contributor.authorLee, JSko
dc.contributor.authorSim, JYko
dc.contributor.authorPark, HJko
dc.date.available2016-04-01T02:59:40Z-
dc.date.created2011-04-18-
dc.date.issued2009-08-
dc.identifier.citationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.56, no.8, pp.1645 - 1656-
dc.identifier.issn1549-8328-
dc.identifier.other2009-OAK-0000020951-
dc.identifier.urihttp://oasis.postech.ac.kr/handle/2014.oak/26103-
dc.description.abstractA 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25-mu m CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 x 120 mu m(2) and 10 mW, respectively, at the data rate of 2 Gb/s.-
dc.description.statementofresponsibilityX-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDecision-feedback equalization (DFE)-
dc.subjectDRAM interface-
dc.subjectequalizer-
dc.subjectintegration-
dc.subjectintersymbol interference (ISI)-
dc.subjectmultidrop bus-
dc.subjectsingle-ended signaling-
dc.subjectstubless channel-
dc.subjectDECISION-FEEDBACK EQUALIZER-
dc.subjectLOW-POWER-
dc.subjectSERIAL LINK-
dc.subjectDDR3 SDRAM-
dc.subjectINTERFACE-
dc.subjectDRAM-
dc.subjectTRANSCEIVER-
dc.subjectBACKPLANE-
dc.subjectSCHEME-
dc.subjectBUS-
dc.titleA 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling-
dc.typeArticle-
dc.contributor.college정보전자융합공학부-
dc.identifier.doi10.1109/TCSI.2008.2010099-
dc.author.googleBae, SJ-
dc.author.googleChi, HJ-
dc.author.googleSohn, YS-
dc.author.googleLee, JS-
dc.author.googleSim, JY-
dc.author.googlePark, HJ-
dc.relation.volume56-
dc.relation.issue8-
dc.relation.startpage1645-
dc.relation.lastpage1656-
dc.contributor.id10071836-
dc.publisher.locationUS-
dc.relation.journalIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.relation.indexSCI급, SCOPUS 등재논문-
dc.relation.sciSCI-
dc.collections.nameJournal Papers-
dc.type.rimsART-
dc.contributor.localauthorSim, JY-
dc.contributor.nonIdAuthorBae, SJ-
dc.contributor.nonIdAuthorChi, HJ-
dc.contributor.nonIdAuthorSohn, YS-
dc.contributor.nonIdAuthorLee, JS-
dc.contributor.nonIdAuthorPark, HJ-
dc.identifier.wosid000269213400003-
dc.date.tcdate2019-02-01-
dc.citation.endPage1656-
dc.citation.number8-
dc.citation.startPage1645-
dc.citation.titleIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.citation.volume56-
dc.identifier.scopusid2-s2.0-69449108028-
dc.description.journalClass1-
dc.description.wostc12-
dc.description.scptc11*
dc.date.scptcdate2018-05-121*

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심재윤SIM, JAE YOON
Dept of Electrical Enginrg
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