A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling

Abstract

A 2-Gb/s integrating decision-feedback equalization (DFE) receiver was implemented for a four-drop single-ended DRAM interface channel by using a 0.25-mu m CMOS process. The receiver combines both DFE and integration operations in a single receiver circuit so that the DFE operation reduces the intersymbol interference and the integration operation reduces the high-frequency noise. The DFE operation was implemented by switching the capacitance values of the two output nodes of a differential integrator, depending on the previous decision data. A look-ahead scheme was used to reduce the DFE loop delay. A MUX-embedded D flip-flop was used in the look-ahead circuit to further reduce the DFE loop delay and latency. The DFE operation enhanced the voltage margins by 110% and 90% at the 2-Gb/s stubless channel and the 1.2-Gb/s stub series terminated logic channel, respectively. The chip area and the power dissipation of the proposed receiver chip were 220 x 120 mu m(2) and 10 mW, respectively, at the data rate of 2 Gb/s.