A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage using VCDL and Time-to-Digital Converter
- Title
- A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage using VCDL and Time-to-Digital Converter
- Authors
- Lee, JS; Sim, JY; Park, HJ; 박홍준
- Date Issued
- 2010-08
- Publisher
- IEICE TRANS. ELECTRON
- Abstract
- A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10 mu m and L = 0.18 mu m in a 16 x 16 array matrix fabricated with a 0.18-mu m process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7 mV and 32.2 mV, respectively, for the temperature range from -25 degrees C to 75 degrees C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10 mV/bit and 3.53 mV/bit at 25 degrees C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125 ns, which corresponds to the 8-MHz throughput.
- Keywords
- on-chip variation monitoring; threshold voltage; time-to-digital converter (TDC); voltage controlled delay line (VCDL)
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/25817
- DOI
- 10.1587/TRANSELE.E93
- ISSN
- 0916-8524
- Article Type
- Conference
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- There are no files associated with this item.
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