Improving the performance of turbo codes with a simple protection scheme for error-prone bit positions
SCIE
SCOPUS
- Title
- Improving the performance of turbo codes with a simple protection scheme for error-prone bit positions
- Authors
- Oh, WR; Kim, YH; Cheun, KW
- Date Issued
- 2005-11
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGI
- Abstract
- It is well known that turbo codes provide highly unequal error protection within a transmitted frame. Previous attempts to exploit this fact focused mainly on adding additional redundancy to provide extra protection for the error-prone bit positions. Here, instead, we use the error-detection capability of the cyclic redundancy check (CRC), which is almost always employed in practical systems. Once a frame is declared uncorrectable by the CRC, a process termed the error-prone bit processing procedure is activated in an attempt to correct the probable error patterns which are a priori identified as being error-prone.
- Keywords
- cyclic redundancy check (CRC); iterative decoding; turbo codes; LIST
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/24299
- DOI
- 10.1109/TCOMM.2005.858653
- ISSN
- 0090-6778
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 53, no. 11, page. 1777 - 1781, 2005-11
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- There are no files associated with this item.
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