A three-data differential signaling over four conductors with pre-emphasis and equalization: A CMOS current mode implementation
SCIE
SCOPUS
- Title
- A three-data differential signaling over four conductors with pre-emphasis and equalization: A CMOS current mode implementation
- Authors
- Choi, SW; Lee, HB; Park, HJ
- Date Issued
- 2006-03
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGI
- Abstract
- A current-mode differential signaling of three data over two pairs of transmission lines increases the effective maximum data rate per pair of transmission lines by about 37% over the conventional pure differential signaling. Each of two data is transmitted as a half-swing differential signal over a pair of transmission lines. The third data is transmitted as a half-swing complementary common-mode signal of the two pairs of transmission lines. Both a single-tap pre-emphasis and a single-tap decision feedback equalizer are combined with this work. Adding a D flip-flop between the equalizer amplifier and the MUX embedded D flip-flop of receiver enables 4-Gb/s operation of receiver. The chip fabricated by using a 0.25-mu m CMOS process shows the maximum data rates of 4 and 3.2 Gb/s over 20- and 60-cm-long FR4 transmission lines, respectively, with bit-error rate below 1E-12.
- Keywords
- complementary common-mode; current-mode; differential signaling; look-ahead decision feedback equalization (DFE); MUX embedded D flip-flop; pre-emphasis; three data over four conductors; TRANSMITTER
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/24161
- DOI
- 10.1109/JSSC.2005.864117
- ISSN
- 0018-9200
- Article Type
- Article
- Citation
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 41, no. 3, page. 633 - 641, 2006-03
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