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Weighted polynomial digital predistortion for low memory effect Doherty power amplifier SCIE SCOPUS

Title
Weighted polynomial digital predistortion for low memory effect Doherty power amplifier
Authors
Hong, SCWoo, YYKim, JCha, JKim, IMoon, JYi, JKim, B
Date Issued
2007-05
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGI
Abstract
We have proposed a simple and effective weighted polynomial digital predistortion algorithm, which consists of weighting, least square polynomial fit, and de-weighting. The weighting factor is introduced to describe the signal distribution statistics and high harmonic generation at a high power region to improve accuracy of the error function. A low memory linear Doherty power amplifier (PA) has been realized with two 90-W peak envelope power LDMOSFETs using memory effect reduction techniques, and the proposed algorithm has been applied to the PA. For the forward-link wideband code division multiple access 3FA signal, the adjacent channel leakage ratio performance at 5-MHz offset is -56 dBc with power-added efficiency of 20.78% at an average power of 40 dBm. The proposed weighting polynomial algorithm provides a significantly reduced error power and superior convergence behavior with improved linearization capability than the conventional polynomial. Moreover, the low memory Doherty amplifier could be linearized for a wideband signal using the simple algorithm without any memory effect compensation.
Keywords
digital predistortion (DPD); Doherty; linearization; memory effect; power amplifier (PA); weighted polynomial; LINEARIZATION; TRANSMITTERS; DESIGN; RF
URI
https://oasis.postech.ac.kr/handle/2014.oak/23398
DOI
10.1109/TMTT.2007.895167
ISSN
0018-9480
Article Type
Article
Citation
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, vol. 55, no. 5, page. 925 - 931, 2007-05
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김범만KIM, BUM MAN
Dept of Electrical Enginrg
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