A low-power implementation of asynchronous 8051 employing adaptive pipeline structure
SCIE
SCOPUS
- Title
- A low-power implementation of asynchronous 8051 employing adaptive pipeline structure
- Authors
- Lee, JH; Kim, YH; Cho, KR
- Date Issued
- 2008-07
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGI
- Abstract
- This paper presents a low-power implementation of the A8051 processor. It employs an adaptive pipeline structure that allows to skip a redundant stage operation and to combine with the neighboring empty stage. The processor has three features to reduce the power dissipation as well as to improve performance: multilooping control for multicycle instructions, branch predictor for unconditional branches, and a single threading in the EXE stage. The experimental results show that A8051 runs about 1.8 times faster than the synchronous counterpart, CIP51 [reported in the HC8051F0xx Family Datasheet (2002)]. In terms of Et-2, our implementation shows 15 times higher efficiency than that of asynchronous counterpart developed by the Nanyang University [Chang and Gwee (2006)].
- Keywords
- asynchronous logic circuits; computer architecture; microprocessor; pipelines; power analysis
- URI
- https://oasis.postech.ac.kr/handle/2014.oak/22486
- DOI
- 10.1109/TCSII.2008.9
- ISSN
- 1549-7747
- Article Type
- Article
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, vol. 55, no. 7, page. 673 - 677, 2008-07
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