A CMOS CODEC chip for a cost effective Group 4 Fax system

Abstract

A CMOS CODEC chip for image coding and decoding of a Group 4 Fax system was designed, fabricated and tested. The fabricated CODEC chip operates in a parallel pipelined scheme to enhance the throughput and shares a single SRAM chip as a buffer memory with other image processing modules to reduce the system cost. The architecture and the size of coding and decoding LUTs(look up tables) were optimized for the internal 16 bit DSP core used in the CODEC chip. A new algorithm for changing pel(picture element) detection without duplicate data readings from the external buffer memory was adopted to enhance the system speed.